全校師生：
我校定于2019年4月23日舉辦研究生靈犀學(xué)術(shù)殿堂——Paolo Ienne教授報(bào)告會(huì)，現(xiàn)將有關(guān)事項(xiàng)通知如下：
1.報(bào)告會(huì)簡(jiǎn)介
報(bào)告人：Paolo Ienne教授
時(shí)間：2019年4月23日（星期二）上午10: 30
地點(diǎn)：長(zhǎng)安校區(qū)自動(dòng)化學(xué)院二樓學(xué)術(shù)報(bào)告廳（附樓）
報(bào)告題目：High-level Synthesis of Dataflow Circuits from Irregular Software Applications
內(nèi)容簡(jiǎn)介：High-level synthesis (HLS) tools create dedicated circuits from languages such as C and promise to make hardware design accessible, among others, to software programmers targeting configurable platforms. Unfortunately, commercial and academic HLS tools almost universally need expert guidance and generate solutions in the form of statically scheduled datapaths; this implies that circuits out of HLS tools have a hard time exploiting parallelism in code with potential memory dependencies, with control-dependent dependencies in inner loops, or where performance is limited by long latency control decisions. The situation is essentially the same as in computer architecture between Very-Long Instruction Word (VLIW) processors and dynamically scheduled out-of-order superscalar processors; the former display the best performance per cost in highly regular and manually-tuned embedded applications, but general purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. This may be especially true in coming years if broader application classes will need the benefits of reconfigurable hardware acceleration. In this talk, we describe our experiences with dataflow circuits: we present a generic methodology to generate them from C programs, contrast their operation to traditional HLS results, discuss some of their specific challenges, and outline the opportunities they create. (Joint work with Lana Josipovi?, Andrea Guerrieri, et al.)
2.歡迎各學(xué)院師生前來(lái)聽(tīng)報(bào)告。報(bào)告會(huì)期間請(qǐng)關(guān)閉手機(jī)或?qū)⑹謾C(jī)調(diào)至靜音模式。
黨委學(xué)生工作部
自動(dòng)化學(xué)院
2019年4月22日
報(bào)告人簡(jiǎn)介
Paolo Ienne has been a Professor at the EPFL (école polytechnique fédérale de Lausanne，瑞士洛桑聯(lián)邦理工學(xué)院) since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th and at the 24th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012 and 2016, at the 19th International Conference on Field-Programmable Logic and Applications (FPL), in 2009, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, program, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
